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<a href="#define-members">Macros</a> &#124;
<a href="#func-members">Functions</a>  </div>
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<div class="title">xdmaps_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gae19e877d6bba369f3e2e8e806b36f594"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dmaps__v2__1.html#gae19e877d6bba369f3e2e8e806b36f594">XDmaPs_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:gae19e877d6bba369f3e2e8e806b36f594"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write a DMAC register.  <a href="group__dmaps__v2__1.html#gae19e877d6bba369f3e2e8e806b36f594">More...</a><br /></td></tr>
<tr class="separator:gae19e877d6bba369f3e2e8e806b36f594"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the DMAC. </p>
</div></td></tr>
<tr class="memitem:ga93bf462eb200bc133898157d9f846216"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_DS_OFFSET</b>&#160;&#160;&#160;0x000 /* DMA Status Register */</td></tr>
<tr class="separator:ga93bf462eb200bc133898157d9f846216"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d7a3784cb90df8727eb8d9b641c52ea"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_DPC_OFFSET</b>&#160;&#160;&#160;0x004 /* DMA Program Counter Rregister */</td></tr>
<tr class="separator:ga2d7a3784cb90df8727eb8d9b641c52ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac5af210b0cfdc4d966f5f2f72c481118"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_INTEN_OFFSET</b>&#160;&#160;&#160;0X020 /* DMA Interrupt Enable Register */</td></tr>
<tr class="separator:gac5af210b0cfdc4d966f5f2f72c481118"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf5e9b4b7a576ad28f0956df9de5c1107"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_ES_OFFSET</b>&#160;&#160;&#160;0x024 /* DMA Event Status Register */</td></tr>
<tr class="separator:gaf5e9b4b7a576ad28f0956df9de5c1107"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab6f325a35bd281ac14c9c29b35b6129d"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_INTSTATUS_OFFSET</b></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_INTCLR_OFFSET</b>&#160;&#160;&#160;0x02c /* DMA Interrupt Clear Register */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_FSM_OFFSET</b></td></tr>
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<tr class="memitem:ga6b32c35e65f9417be809dadfc916fb6f"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_FSC_OFFSET</b></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_FTM_OFFSET</b>&#160;&#160;&#160;0x038 /* DMA Fault Type DMA Manager Register */</td></tr>
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<tr class="memitem:gafb122a303ab5c60de564753d98416004"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_FTC0_OFFSET</b>&#160;&#160;&#160;0x040 /* DMA Fault Type for DMA Channel 0 */</td></tr>
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<tr class="memitem:gaec1d0f17040328640b3fea0ffd6dc86b"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDmaPs_FTCn_OFFSET</b>(ch)&#160;&#160;&#160;(XDMAPS_FTC0_OFFSET + (ch) * 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CS0_OFFSET</b>&#160;&#160;&#160;0x100 /* Channel Status for DMA Channel 0 */</td></tr>
<tr class="separator:ga1102aea3f454261bc41def53d7e963da"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDmaPs_CSn_OFFSET</b>(ch)&#160;&#160;&#160;(XDMAPS_CS0_OFFSET + (ch) * 8)</td></tr>
<tr class="separator:ga659decc828697a8133122685d54583ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga256c23ca5f031f4cacbabc31f463eddb"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CPC0_OFFSET</b></td></tr>
<tr class="separator:ga256c23ca5f031f4cacbabc31f463eddb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga44da163173636f2136fe796655af9476"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDmaPs_CPCn_OFFSET</b>(ch)&#160;&#160;&#160;(XDMAPS_CPC0_OFFSET + (ch) * 8)</td></tr>
<tr class="separator:ga44da163173636f2136fe796655af9476"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_SA_0_OFFSET</b></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDmaPs_SA_n_OFFSET</b>(ch)&#160;&#160;&#160;(XDMAPS_SA_0_OFFSET + (ch) * 0x20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_DA_0_OFFSET</b></td></tr>
<tr class="separator:gac2853665b08e37e4573447ba7f4c9b6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84df6a5346238f67309c347c44fc0611"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDmaPs_DA_n_OFFSET</b>(ch)&#160;&#160;&#160;(XDMAPS_DA_0_OFFSET + (ch) * 0x20)</td></tr>
<tr class="separator:ga84df6a5346238f67309c347c44fc0611"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga681506ee18097cfa07b6ba5b5beeb866"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CC_0_OFFSET</b></td></tr>
<tr class="separator:ga681506ee18097cfa07b6ba5b5beeb866"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02494d8df0fb7e492045c2cf8501588c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDmaPs_CC_n_OFFSET</b>(ch)&#160;&#160;&#160;(XDMAPS_CC_0_OFFSET + (ch) * 0x20)</td></tr>
<tr class="separator:ga02494d8df0fb7e492045c2cf8501588c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2ca8ff84f1dd985e8a24d31a37467d2"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_LC0_0_OFFSET</b>&#160;&#160;&#160;0x40C /* Loop Counter 0 for DMA Channel 0 */</td></tr>
<tr class="separator:gaf2ca8ff84f1dd985e8a24d31a37467d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad458f37d88fa779f64d69ac8150433d2"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDmaPs_LC0_n_OFFSET</b>(ch)&#160;&#160;&#160;(XDMAPS_LC0_0_OFFSET + (ch) * 0x20)</td></tr>
<tr class="separator:gad458f37d88fa779f64d69ac8150433d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b1724df6582ddd99703cef18721fd26"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_LC1_0_OFFSET</b>&#160;&#160;&#160;0x410 /* Loop Counter 1 for DMA Channel 0 */</td></tr>
<tr class="separator:ga0b1724df6582ddd99703cef18721fd26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fd4d6d9ce6be4a2c13f3126b2b4c7f1"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDmaPs_LC1_n_OFFSET</b>(ch)&#160;&#160;&#160;(XDMAPS_LC1_0_OFFSET + (ch) * 0x20)</td></tr>
<tr class="separator:ga7fd4d6d9ce6be4a2c13f3126b2b4c7f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa916d654a027b1a9089eb95b8324b273"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_DBGSTATUS_OFFSET</b>&#160;&#160;&#160;0xD00 /* Debug Status Register */</td></tr>
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<tr class="memitem:gabd9ff38817fd8a9564f1321beec3d305"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_DBGCMD_OFFSET</b>&#160;&#160;&#160;0xD04 /* Debug Command Register */</td></tr>
<tr class="separator:gabd9ff38817fd8a9564f1321beec3d305"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga56fd2cf1862005e0f2c65f51a2579d30"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_DBGINST0_OFFSET</b>&#160;&#160;&#160;0xD08 /* Debug Instruction 0 Register */</td></tr>
<tr class="separator:ga56fd2cf1862005e0f2c65f51a2579d30"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4323b1b57d49da0e37f7aff6df589b01"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_DBGINST1_OFFSET</b>&#160;&#160;&#160;0xD0C /* Debug Instruction 1 Register */</td></tr>
<tr class="separator:ga4323b1b57d49da0e37f7aff6df589b01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad67a817d020729a0d9966170b0839c9a"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CR0_OFFSET</b>&#160;&#160;&#160;0xE00 /* Configuration Register 0 */</td></tr>
<tr class="separator:gad67a817d020729a0d9966170b0839c9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8067baff7b6942c2d3493631b55c7150"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CR1_OFFSET</b>&#160;&#160;&#160;0xE04 /* Configuration Register 1 */</td></tr>
<tr class="separator:ga8067baff7b6942c2d3493631b55c7150"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6ef3ebf3c2f6352547fb14c9cdb07e7"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CR2_OFFSET</b>&#160;&#160;&#160;0xE08 /* Configuration Register 2 */</td></tr>
<tr class="separator:gaf6ef3ebf3c2f6352547fb14c9cdb07e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ae2d26d9700f665507d7a9f18a51001"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CR3_OFFSET</b>&#160;&#160;&#160;0xE0C /* Configuration Register 3 */</td></tr>
<tr class="separator:ga0ae2d26d9700f665507d7a9f18a51001"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaccda5648ed09d13d4585a3e5e518e29a"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CR4_OFFSET</b>&#160;&#160;&#160;0xE10 /* Configuration Register 4 */</td></tr>
<tr class="separator:gaccda5648ed09d13d4585a3e5e518e29a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga798f21cfa8e02285c78ffa33792e33bd"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CRDN_OFFSET</b>&#160;&#160;&#160;0xE14 /* Configuration Register Dn */</td></tr>
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<tr class="memitem:gadf62309c161914350b7be1bc30b65ff6"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_PERIPH_ID_0_OFFSET</b></td></tr>
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<tr class="memitem:ga6dc2783ea735255f4fe62196b0b1368f"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_PERIPH_ID_1_OFFSET</b></td></tr>
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<tr class="memitem:gadf9dfd7658ae854281b9d433ad0b0dfd"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_PERIPH_ID_2_OFFSET</b></td></tr>
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<tr class="memitem:ga2079a2c939d4acf925b6bdba8b1eb8d6"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_PERIPH_ID_3_OFFSET</b></td></tr>
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<tr class="memitem:ga67d4979c3b3d41bdbfc492f8c47e19c4"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_PCELL_ID_0_OFFSET</b></td></tr>
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<tr class="memitem:ga41b5e2207bc98cce741717e393351f14"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_PCELL_ID_1_OFFSET</b></td></tr>
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<tr class="memitem:gadbfcb068b606b45650477c9db8df5896"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_PCELL_ID_2_OFFSET</b></td></tr>
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<tr class="memitem:gaf90799caf4c2d25e779ee72d7e7e3cbb"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_PCELL_ID_3_OFFSET</b></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_DS_DMA_STATUS</b>&#160;&#160;&#160;0x0F /* DMA status mask */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_DS_DMA_STATUS_STOPPED</b>&#160;&#160;&#160;0x00 /* debug status busy mask */</td></tr>
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<tr class="memitem:gab2e6876678b45b1615220662f5ce5cf1"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_DBGSTATUS_BUSY</b>&#160;&#160;&#160;0x01 /* debug status busy mask */</td></tr>
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<tr class="memitem:ga204e38be7430f0077f3eb9468a351bbe"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CS_ACTIVE_MASK</b></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPS_CR1_I_CACHE_LEN_MASK</b>&#160;&#160;&#160;0x07 /* i_cache_len mask */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDmaPs_DBGINST0</b>(b1,  b0,  ch,  dbg_th)&#160;&#160;&#160;(((b1) &lt;&lt; 24) | ((b0) &lt;&lt; 16) | (((ch) &amp; 0x7) &lt;&lt; 8) | ((dbg_th &amp; 0x1)))</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga1979923efe3208602a8e4ba6ff2aff32"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dmaps__v2__1.html#ga1979923efe3208602a8e4ba6ff2aff32">XDmaPs_ResetHw</a> (u32 BaseAddress)</td></tr>
<tr class="memdesc:ga1979923efe3208602a8e4ba6ff2aff32"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function perform the reset sequence to the given dmaps interface by configuring the appropriate control bits in the dmaps specifc registers the dmaps reset squence involves the following steps Disable all the interuupts Clear the pending interrupts Kill all the active channel threads Kill the manager thread.  <a href="group__dmaps__v2__1.html#ga1979923efe3208602a8e4ba6ff2aff32">More...</a><br /></td></tr>
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